Method of reducing sti divot formation during semi

由于STI corner处的Oxide应力较大，所以在HF蚀刻过程中吃的比较快，所以很容易凹下去形成divot，而这里的Poly depo时候也容易凹下去，所以Gate电场在这里会发生变化，导致此处的 ...

但由于局部应力集中，很容易会在sti界面处(sio2接近硅的有源区域)的角边缘过度腐蚀填充的氧化层而形成一凹陷区，一般称为“divot”。这种“divot”现象导致 ...

There are 3~5% performance improvement by STI divot increased around 30A of Core device nominal P and SRAM PU was been shown on 28nm HKMG platform. And the GOI ...

The SiN pull-back process is known for reducing divot around the top comer in conventional STI. Both LOCOS and PB-STI can result in divot free. It is also ...

在去除氮化矽與墊氧化矽，及其. 它濕式處理程序時，可能由於局部應力的集中之故，容易過度蝕刻接近. 隔離邊緣的充填氧化層而形成一凹陷區，一般稱為Divot。當閘極跨過隔. 離 ...

本研究探討場發射金屬氧化半導電晶體（MOSFET）淺溝槽隔離絕緣層（Shallow Trench Isolation，STI）與鄰近電晶體主動區的高度差（Step-height）對元件特性的影響。

1355678 % • 九、發明說明： 【發明所屬之技術領域】 • · 本發明係關於製造積體電路半導體裝置。本發明尤其可應用於製造具有高品質淺溝隔離（STI)而不具有或具有貫質減少 ...

STI divot formation is eliminated or substantially reduced by employing a very thin nitride polish stop layer, e.g., no thicker than 400 Å. The very thin ...

This paper will discuss the effect of etching methods for the STI divot feature and the impact of divot depth on the performance of 28m HKMG logic devices ...